1. Technical Field
The inventive concept relates to a semiconductor device, and more particularly, to a variable resistive memory device including a memory cell array.
2. Related Art
Portable digital apparatuses have been spread day by day. Ultra-high integration, ultra-high speed, and ultra-low power consumption are required to memory devices embedded in the portable digital apparatuses for processing large-capacity data with higher speed, although the memory devices have a limited size.
To meet the demands, vertical memory devices have been actively researched. Three-dimensional (3D) vertical gate structures have been applied to resistive memory devices which are considered as one of next-generation memory devices.
The resistive memory devices are configured to select a cell through an access device and change a resistance of a data storage material electrically connected to the access device to store data. As the resistive memory devices, there are phase-change memory devices, resistive memory devices, magnetoresistive memory devices, and the like.
The resistive memory device may employ a diode or a transistor as the access device. In particular, the thresh voltage of the transistor may be lowered as compared with the diode. Thus, the transistor can reduce an operation voltage. As the transistor can be fabricated in a vertical structure, the transistor has received attention again as the access device of the resistive memory device.
That is, since a voltage of 1.1 V or more has to be applied to the diode, there is a limit to lower the operation voltage. Further, when the diode is formed on the word line, resistance of the word line is changed according to positions of cells. Thus, a word line bouncing issue occurs.
Since the transistor generally has a horizontal structure in the related art, there is a limit to increase an integration degree of device. However, unlike a horizontal structure, the vertical transistor may sufficiently ensure current drivability in the limited channel area.
FIG. 1 is a layout diagram schematically illustrating a general 3D variable resistive memory device.
Referring to FIG. 1, a plurality of active pillars 20 are regularly arranged on a semiconductor substrate in a row and column directions. The active pillars 20 are configured to have a line width of 1 F (minimum feature size) in width and length. The active pillars 20 are arranged to have a distance of 0.5 F in a column direction and a distance of 1.5 F in a row direction. A word line 30 is arranged on active pillars 20 positioned in the same column. The word line 30 may be arranged to entirely surround the active pillar 20 to have a line width of 2 F. Further, the word line 30 may be spaced by an interval of 0.5 F to be insulated from an adjacent word line 30.
As shown in FIGS. 2 and 3, the word line 30 is arranged between the active pillars 20 in the column direction and the word lines 30 are spaced from each other by a distance S in the column direction. Here, the reference numeral 10 denotes a semiconductor substrate, and the reference numeral 15 denotes a common source electrode.
In the related art, the active pillars 20 are arranged to be surrounded by the word line 30. Thus, the distance between the active pillars 20 may be reduced in an extension direction of the word line. However, there may be still a limit to reduce the distance between the active pillars in the row direction.